1. Technical Field
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit having a state saving latch.
2. Related Art
With the increasing popularity of portable electronic devices, such as laptops, cell phones and personal digital assistants (PDA""s), there is a growing need for systems that can reduce power consumption in order to extend energy storage times of the device""s power supply (e.g., battery). Namely, applications that utilize CMOS integrated circuits (IC""s) require circuits that utilize a minimal amount of power and have the capability to be powered down when not in use.
Many electronic devices, including systems having custom and application specific IC""s (ASIC) feature some form of standby, sleep, or low power modexe2x80x94referred to collectively herein as sleep mode. These modes exhibit greatly reduced power dissipation by essentially disconnecting some of the logic in the device from the power supply when the logic is not required. Powering down portions of an IC cannot only be used to save power and extend battery life, but can be used in certain schemes to manage chip power in systems operating from a standard power supply.
Recovery from sleep mode generally requires returning the IC to the state it was in just prior to entering sleep mode. However, without power, storage elements in an IC will lose their stored bits of information. Accordingly, for commonly used elements, such as data latches, the stored value in the latch must be maintained when the IC is switched to sleep mode and be restored after power-up. Accordingly, a need exists for circuitry that can save the state of a latch before power-down, and restore the state of the latch after power-up.
The present invention addresses the above-mentioned problems, as well as others, by providing a circuit having a state saving mode of operation. In a first aspect, the invention provides a state saving circuit, comprising: a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being maintained in the first latch.
In a second aspect, the invention provides a method of saving a state in a circuit, comprising: providing a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for cutting off input into the first latch; providing a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a clock input for latching the data from the first latch to the second latch; inputting and storing data in the first latch; activating the input cut-off control to cut off further input into the first latch; and interrupting the power supply to the second latch.
In a third aspect, the invention provides a system having a power down mode for managing power consumption, the system having a state saving circuit, comprising: a first latch powered by an uninterruptible power supply, wherein the first latch includes a data input for receiving data and a storage circuit for storing received data; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a clock input for latching the data from the first latch to the second latch; and an input cut-off control for isolating data in the first latch by preventing further data from being inputted to the first latch, wherein the input cut-off control is activated when power to the interruptible power supply is cut off.